BECKHOFF EtherCAT IP Core for Xilinx FPGAs v3.00k - Manual (Page 99)

Ethernet Interface
Slave Controller – IP Core for Xilinx FPGAs III-87
9.4 RGMII Interface
The IP Core supports RGMII with1-3 communication ports at 100 Mbit/s. Nevertheless, MII is
recommended since the PHY delay (and delay jitter) is smaller in comparison to RGMII.
The RGMII interface of the EtherCAT IP Core offers signals for attaching DDR input and output cells,
which have to be added by the IP Core user. This approach offers maximum flexibility for the
implementation, which is required because RGMII has tight timing requirements. Please refer to Xilinx
for implementation and constraining guidelines.
The Beckhoff ESCs have additional requirements to Ethernet PHYs using RGMII, which are easily
accomplished by several PHY vendors.
Refer to “Section I – Technology” for Ethernet PHY requirements.
Additional information regarding the IP Core:

The signal polarity of nRGMII_LINK is not configurable inside the IP Core, nRGMII_LINK is active
low. If necessary, the signal polarity must be swapped outside the IP Core.

The IP Core can be configured to use the MII management interface for link detection and link
configuration.

The IP Core supports arbitrary PHY addresses.

A Gigabit Ethernet PHY has to be restricted to establish only 100 Mbit/s links (e.g. by using MI link
detection and configuration).
For details about the ESC RGMII Interface refer to Section I.
9.4.1 RGMII Interface Signals
The RGMII interface of the IP Core has the following signals: