BECKHOFF EtherCAT IP Core for Xilinx FPGAs v3.00k - Manual (Page 142)

Synthesis Constraints
III-130 Slave Controller – IP Core for Xilinx FPGAs
Example User Constraints File (UCF)
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### Global CLK/Reset ###
########################
### Clock source 25 MHz/40 ns ###
TIMESPEC TS_REF_CLK = PERIOD TM_REF_CLK 40000 ps;
Net REF_CLK TNM_NET = TM_REF_CLK;
### Reset ###
Net nRESET TIG;
##################
### MII Port 0 ###
##################
### Receive clock period 40 ns/25 MHz ###
TIMESPEC TS_RX_CLK0 = PERIOD TM_RX_CLK0 40000 ps;
Net MII_RX_CLK0 TNM_NET = TM_RX_CLK0;
### RX_DV/RX_DATA setup 10 ns, hold 10 ns ###
OFFSET = IN 10 ns VALID 20 ns BEFORE MII_RX_CLK0;
### TX_ENA/TX_DATA maximum clock-to-pad 10 ns ###
### (manually check minimum clock-to-pad = 0 ns) ###
### TX_CLK from PHY to REF_CLK phase shift has to be ###
### determined and compensated using TX-Shift or registers ###
TIMEGRP TM_TX0 OFFSET = OUT 10 ns AFTER REF_CLK;
Net MII_TX_ENA0 TNM_NET=TM_TX0;
Net MII_TX_DATA0<0> TNM_NET=TM_TX0;
Net MII_TX_DATA0<1> TNM_NET=TM_TX0;
Net MII_TX_DATA0<2> TNM_NET=TM_TX0;
Net MII_TX_DATA0<3> TNM_NET=TM_TX0;
##################
### MII Port 1 ###
##################
### Receive clock period 40 ns/25 MHz ###
TIMESPEC TS_RX_CLK1 = PERIOD TM_RX_CLK1 40000 ps;
Net MII_RX_CLK1 TNM_NET = TM_RX_CLK1;
### RX_DV/RX_DATA setup 10 ns, hold 10 ns ###
OFFSET = IN 10 ns VALID 20 ns BEFORE MII_RX_CLK1;
### TX_ENA/TX_DATA maximum clock-to-pad 10 ns ###
### (manually check minimum clock-to-pad = 0 ns) ###
### TX_CLK from PHY to REF_CLK phase shift has to be ###
### determined and compensated using TX-Shift or registers ###
TIMEGRP TM_TX1 OFFSET = OUT 10 ns AFTER REF_CLK;
Net MII_TX_ENA1 TNM_NET=TM_TX1;
Net MII_TX_DATA1<0> TNM_NET=TM_TX1;
Net MII_TX_DATA1<1> TNM_NET=TM_TX1;
Net MII_TX_DATA1<2> TNM_NET=TM_TX1;
Net MII_TX_DATA1<3> TNM_NET=TM_TX1;