BECKHOFF EtherCAT IP Core for Xilinx FPGAs v3.00k - Manual (Page 24)

Overview
III-12 Slave Controller – IP Core for Xilinx FPGAs
1.10 Simulation
A behavioral simulation model of the EtherCAT IP core is not available because of its size and
complexity. Thus, simulation of the entire EtherCAT IP Core is not supported. In most cases,
simulation of the EtherCAT IP Core is not necessary, as the IP Core was thoroughly tested and the
interfaces are standardized (Ethernet, PLB, AXI) or simple and well described. Problems at the
interface level can often be solved with a scope shot of the interface signals.
Nevertheless, customer designs using the PLB or AXI on-chip bus can easily be simulated using a
Bus Functional Model of the on-chip bus slave interface instead of a simulation model of the entire
EtherCAT IP Core.
From the processor’s view, the EtherCAT IP Core is a memory (or a bunch of registers). For processor
bus verification, the EtherCAT IP Core can be substituted by another IP core with PLB/AXI slave
interface which behaves like a memory as well. The EtherCAT IP Core can be replaced for simulation
by e.g.:

Xilinx XPS Block RAM (BRAM) Interface Controller with a Block RAM block
 PLB Bus Functional models of the “IBM On-Chip Bus Model Toolkits”. This toolkit can be used for
complete verification of your PLB bus interfaces.

AXI slave Bus Functional models