BECKHOFF EtherCAT IP Core for Xilinx FPGAs v3.00k - Manual (Page 28)

Features and Registers
III-16 Slave Controller – IP Core for Xilinx FPGAs
2.2 Registers
An EtherCAT Slave Controller (ESC) has an address space of 64KByte. The first block of 4KByte
(0x0000:0x0FFF) is dedicated for registers. The process data RAM starts at address 0x1000, its size
is configurable.
Some registers are implemented depending on the configuration.
Table 9 gives an overview of the available registers.
Table 9: Register availability
Address Length
(Byte) Description IP Core
V3.00c-
V3.00k
0x0000 1 Type x
0x0001 1 Revision x
0x0002:0x0003 2 Build x
0x0004 1 FMMUs supported x
0x0005 1 SyncManagers supported x
0x0006 1 RAM Size x
0x0007 1 Port Descriptor x
0x0008:0x0009 2 ESC Features supported x
0x0010:0x0011 2 Configured Station Address x
0x0012:0x0013 2 Configured Station Alias x
0x0020 1 Write Register Enable c
0x0021 1 Write Register Protection c
0x0030 1 ESC Write Enable c
0x0031 1 ESC Write Protection c
0x0040 1 ESC Reset ECAT c
0x0041 1 ESC Reset PDI c
0x0100:0x0101 2 ESC DL Control x
0x0102:0x0103 2 Extended ESC DL Control x
0x0108:0x0109 2 Physical Read/Write Offset c
0x0110:0x0111 2 ESC DL Status x
0x0120 5 bits
[4:0]
AL Control x
0x0120:0x0121 2 AL Control x
0x0130 5 bits
[4:0]
AL Status x
0x0130:0x0131 2 AL Status x
0x0134:0x0135 2 AL Status Code c
0x0138 1 RUN LED Override c
0x0139 1 ERR LED Override c
0x0140 1 PDI Control x
0x0141 1 ESC Configuration x
0x014E:0x014F 2 PDI Information c
0x0150 1 PDI Configuration x
0x0151 1 DC Sync/Latch Configuration x
0x0152:0x0153 2 Extended PDI Configuration x
0x0200:0x0201 2 ECAT Event Mask x
0x0204:0x0207 4 PDI0 AL Event Mask r/c