BECKHOFF EtherCAT IP Core for Xilinx FPGAs v3.00k - Manual (Page 130)

PDI Description
III-118 Slave Controller – IP Core for Xilinx FPGAs
Signal Direction Description Signal polarity
PLB_IRQ_MAIN OUT Interrupt act. high
Please refer to the “128-bit Processor Local Bus Architecture Specifications” from IBM (publication
number SA-14-2538-04) for details about the PLB bus (
http://www.ibm.com ).
10.4.2 Configuration
The PLB v4.6 interface has PDI type 0x80 in the PDI control register 0x0140. The PLB PDI has no
configuration options in the IP Core configuration utility. Some parameters are passed to the PLB PDI
via VHDL generics, they are typically configured in the Xilinx EDK. The PLB PDI supports a fixed data
bus width of 32 and it requires byte enables.
Address Range (C_BASEADDR and C_HIGHADDR)
The address range of the EtherCAT IP Core PLB slave is defined with two VHDL generics
C_BASEADDR (holding the base address) and C_HIGHADDR (containing the end address). The
address range of the EtherCAT IP core should span at least 64 Kbyte (e.g., C_BASEADDR =
0x00010000 and C_HIGHADDR=0x0001FFFF). A larger address range results in less address
decoding logic.
Bus Clock Period (C_SPLB_CLK_PERIOD_PS)
The PLB bus clock period is set by the Xilinx EDK depending on the clock source configuration. This
value is passed to the EtherCAT IP core with the VHDL generic C_SPLB_CLK_PERIOD_PS.
There are two options for the PLB bus clock, either it is synchronous with the IP core or asynchronous.
If it is synchronous, the PLB bus clock has to be an integer multiple of 25 MHz, and the rising edges of
CLK25 and PLB_SPLB_Clk have to by synchronized. In the asynchronous case, the PLB bus clock
has to be faster than CLK25.
The EtherCAT IP Core distinguishes between synchronous and asynchronous PLB bus clock based
on the value of C_SPLB_CLK_PERIOD_PS. If this value corresponds with a synchronous frequency
(N*25 MHz), synchronous clocking is assumed, otherwise asynchronous clocking is assumed.
The following table gives an overview of C_SPLB_CLK_PERIOD_PS values which make the
EtherCAT IP Core assume synchronous clocking.
Table 59: PLB clock period values for synchronous clocking
C_SPLB_CLK_PERIOD_PS PLB_SPLB_Clk frequency
40,000 25 MHz
20,000 50 MHz
13,333 or 13,334 75 MHz
10,000 100 MHz
8,000 125 MHz
6,666 or 6,667 150 MHz
5,714 or 5,715 175 MHz
5,000 200 MHz
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