FIGURES
Slave Controller
– IP Core for Xilinx FPGAs
III-XI
Figure 61: AXI Read Access ............................................................................................................... 125
Figure 62: AXI Write Access ................................................................................................................ 125
Figure 63: Distributed Clocks signals .................................................................................................. 126
Figure 64: LatchSignal timing .............................................................................................................. 126
Figure 65: SyncSignal timing ............................................................................................................... 126
Figure 66: I²C EEPROM signals .......................................................................................................... 127