2 features and registers, 1 features, Features and registers – BECKHOFF EtherCAT IP Core for Xilinx FPGAs v3.00k User Manual
Page 25: Features, Table 7: ip core feature details, 2features and registers
Features and Registers
Slave Controller
– IP Core for Xilinx FPGAs
III-13
2
Features and Registers
2.1
Features
Table 7: IP Core Feature Details
Feature
IP Core
Xilinx
®
V3.00k
IP Core
Xilinx
®
V3.00c-
3.00j
EtherCAT Ports
1-3
1-3
Permanent ports
1-3
1-3
Optional Bridge port 3 (EBUS or
MII)
-
-
EBUS ports
-
-
MII ports
0-3
0-3
RMII ports
0-2
0-2
RGMII ports
0-3
0-3
Port 0
x
x
Ports 0, 1
x
x
Ports 0, 1, 2
x
x
Ports 0, 1, 3
-
-
Ports 0, 1, 2, 3
-
-
EtherCAT mode
Direct
Direct
Slave Category
Full Slave
Full Slave
Position addressing
x
x
Node addressing
x
x
Logical addressing
x
x
Broadcast addressing
x
x
Physical Layer General Features
FIFO Size configurable
(0x0100[18:16])
x
x
FIFO Size default from SII
EEPROM
x
x
Auto-Forwarder checks CRC and
SOF
x
x
Forwarded RX Error indication,
detection and Counter
(0x0308:0x030B)
x
x
Lost Link Counter
(0x0310:0x0313)
c
c
Prevention of circulating frames
x
x
Fallback: Port 0 opens if all ports
are closed
x
x
VLAN Tag and IP/UDP support
x
x
Enhanced Link Detection per port
configurable
x
x
General Ethernet Features
(MII/RMII/RGMII)
MII Management Interface
(0x0510:0x051F)
c
c
Supported PHY Address Offsets
any
any
Individual port PHY addresses
x
x
Port PHY addresses readable
x
x
Link Polarity configurable
User logic
User logic
Enhanced Link Detection
supported
x
x
FX PHY support (native)
x
x
PHY reset out signals
x
x
Link detection using PHY signal
(LED)
x
x
MI link status and configuration
c
c
MI controllable by PDI
(0x0516:0x0517)
x
x
MI read error (0x0510.13)
x
x
MI PHY configuration update
status (0x0518.5)
x
x
MI preamble suppression
x
x
Additional MCLK
x
x
Gigabit PHY configuration
x
x
Gigabit PHY register 9 relaxed
check
x
x
FX PHY configuration
x
x
Transparent Mode
-
-
Feature
IP Core
Xilinx
®
V3.00k
IP Core
Xilinx
®
V3.00c-
3.00j
MII Features
CLK25OUT as PHY clock source
User logic
User logic
Bootstrap TX Shift settings
c
c
Automatic TX Shift setting (with
TX_CLK)
c
c
TX Shift not necessary (PHY
TX_CLK as clock source)
-
-
FIFO size reduction steps
2
2
PDI General Features
Increased PDI performance
x
x
Extended PDI Configuration
(0x0152:0x0153)
x
x
PDI Error Counter (0x030D)
c
c
PDI Error Code (0x030E)
c
c
CPU_CLK output (10, 20, 25
MHz)
User logic
User logic
SOF, EOF, WD_TRIG and
WD_STATE independent of PDI
x
x
Available PDIs and PDI features
depending on port configuration
-
-
PDI selection at run-time (SII
EEPROM)
-
-
PDI active immediately (SII
EEPROM settings ignored)
x
x
PDI function acknowledge by
write
c
c
PDI Information register
0x014E:0x014F
c
c
Digital I/O PDI
x
x
Digital I/O width [bits]
8/16/24/32
8/16/24/32
PDI Control register value
(0x0140:0x0141)
4
4
Control/Status signals:
7
7
LATCH_IN
x
x
SOF
x
x
OUTVALID
x
x
WD_TRIG
x
x
OE_CONF
-
-
OE_EXT
x
x
EEPROM_
Loaded
x
x
WD_STATE
x
x
EOF
x
x
Granularity of direction
configuration [bits]
8
8
Bidirectional mode
- (User
logic)
- (User
logic)
Output high-Z if WD expired
User logic
User logic
Output 0 if WD expired
x
x
Output with EOF
x
x
Output with DC SyncSignals
x
x
Input with SOF
x
x
Input with DC SyncSignals
x
x
SPI Slave PDI
x
x
Max. SPI clock [MHz]
30
30
SPI modes configurable
(0x0150[1:0])
x
x
SPI_IRQ driver configurable
(0x0150[3:2])
x
x
SPI_SEL polarity configurable
(0x0150.4)
x
x
Data out sample mode
configurable (0x0150.5)
x
x
Busy signaling
-
-