BECKHOFF EtherCAT IP Core for Xilinx FPGAs v3.00k - Manual (Page 65)

Example Designs
Slave Controller – IP Core for Xilinx FPGAs III-53
6.2.3 Implementation
1. Open Xilinx EDK
2. Open project:
<IPInst_dir>\ example_designs\LX150T_AXI\system.xmp
3. Generate Bitstream
4. Export Design
5. Launch SDK
6. In SDK, select menu File
– New – Application Project
7. Enter a project name, and select project template “BECKHOFF EtherCAT LX150T AXI”
8. Select Next, then Finish.
9. Wait until the projects are built automatically, or select menu Project
– Build All
10. Update Bitstream with application image and download to FPGA by selecting menu Xilinx Tools –
Program FPGA

Result is the file “download.bit” (= “system.bit” + “<application>.elf”) in the implementation
folder of the EDK project.
6.2.4 SII EEPROM
Use this ESI for the SII EEPROM:
Beckhoff Automation GmbH (Evaluation)/
IP Core example designs ET1815 (Xilinx)/
ET1815 IP Core Avnet LX150T
6.2.5 Downloadable configuration file
An already synthesized time limited configuration file
LX150T_AXI_Demo_V3_00c_time_limited.bit
based on this example design can be found in the
<IPInst_dir>\example_designs\LX150T_AXI\
folder. After expiration of about 1 hour the design quits its operation. These files must only be used for
evaluation purposes, any distribution is not allowed.