BECKHOFF EtherCAT IP Core for Xilinx FPGAs v3.00k - Manual (Page 82)

IP Core Signals
III-70 Slave Controller – IP Core for Xilinx FPGAs
8.6 PDI Signals
8.6.1 General PDI Signals
Table 27 lists the signals available independent of the PDI configuration.
Table 26: General PDI Signals
Condition Name Direction Description
PDI_SOF OUTPUT
Ethernet Start-of-Frame if
1
PDI_EOF OUTPUT Ethernet End-of-Frame if 1
PDI_WD_TRIGGER OUTPUT
Process Data Watchdog
trigger if 1
PDI_WD_STATE OUTPUT
Process Data Watchdog
state
0:
Expired
1: Not expired
GPIO Bytes > 0 PDI_GPI[8*Bytes-1:0] INPUT
General purpose inputs
(width configurable, 1/2/4/8
Bytes)
GPIO Bytes > 0 PDI_GPO[8*Bytes-1:0] OUTPUT
General purpose outputs
(width N:0 configurable,
1/2/4/8 Bytes)
8.6.2 Digital I/O Interface
Table 27 lists the signals used with the Digital I/O PDI.
Table 27: Digital I/O PDI
Condition Name Direction Description
Byte 0 is Output PDI_DIGI_DATA_OUT0 [7:0] OUTPUT Digital output byte 0
Byte 0 is Input PDI_DIGI_DATA_IN0 [7:0] INPUT Digital input byte 0
Byte 1 is Output PDI_DIGI_DATA_OUT1[7:0] OUTPUT Digital output byte 1
Byte 1 is Input PDI_DIGI_DATA_IN1[7:0] INPUT Digital input byte 1
Byte 2 is Output PDI_DIGI_DATA_OUT2[7:0] OUTPUT Digital output byte 2
Byte 2 is Input PDI_DIGI_DATA_IN2[7:0] INPUT Digital input byte 2
Byte 3 is Output PDI_DIGI_DATA_OUT3 [7:0] OUTPUT Digital output byte 3
Byte 3 is Input PDI_DIGI_DATA_IN3[7:0] INPUT Digital input byte 3
If both, digital input and
output selected
PDI_DIGI_DATA_ENA OUTPUT Digital output enable
any digital input
selected and Input
mode=Latch with ext.
signal
PDI_DIGI_LATCH_IN INPUT
Latch digital input at rising
edge
any digital output
selected
PDI_DIGI_OE_EXT INPUT External output enable
PDI_DIGI_OUTVALID OUTPUT Output event: output valid