BECKHOFF EtherCAT IP Core for Xilinx FPGAs v3.00k - Manual (Page 92)

Ethernet Interface
III-80 Slave Controller – IP Core for Xilinx FPGAs
9.2 MII Interface
The MII interface of the IP Core is optimized for low processing/forwarding delays by omitting a
transmit FIFO. To allow this, the IP Core has additional requirements to Ethernet PHYs, which are
easily accomplished by several PHY vendors.
Refer to “Section I – Technology” for Ethernet PHY requirements.
Additional information regarding the IP Core:

The clock source of the PHYs is the same as for the FPGA (25 MHz quartz oscillator)

The signal polarity of nMII_LINK is not configurable inside the IP Core, nMII_LINK is active low. If
necessary, the signal polarity must be swapped by user logic outside the IP Core.

The IP Core can be configured to use the MII management interface for link detection and link
configuration.

The IP Core supports arbitrary PHY addresses
For details about the ESC MII Interface refer to Section I.