BECKHOFF EtherCAT IP Core for Xilinx FPGAs v3.00k - Manual (Page 137)

PDI Description
Slave Controller – IP Core for Xilinx FPGAs III-125
CLK_PDI_EXT
ARREADY
ADR ARADR
RVALID
RDATA DATA
t Read
ARVALID
t
Clk
Figure 61: AXI Read Access
CLK_PDI_EXT
AWREADY
WREADY
ADR
DATA
AWADR
WDATA
BVALID
t Write
AWVALID
WVALID
t
Clk
Figure 62: AXI Write Access