BECKHOFF EtherCAT IP Core for Xilinx FPGAs v3.00k - Manual (Page 52)

IP Core Configuration
III-40 Slave Controller – IP Core for Xilinx FPGAs
5.1.4 Feature Details tab
Figure 16: Feature Details tab
Read/Write Offset
Physical Read/Write Offset (0x00108:0x0109) is available if checked.
Write Protection
Register write protection and ESC write protection (0x0020:0x0031) are available if checked.
AL Status Code Register
AL Status Code register (0x0134:0x0135) is available if checked.
Extended Watchdog
Watchdog Divider (0x0400:0x0401) is configurable and PDI Watchdog (0x0410:0x0411, and
0x0100.1) is available if checked.
AL Event Mask Register
AL Event Mask register (0x0204:0x0207) is available if checked.
Watchdog Counter
Watchdog Counters (0x0442:0x0443) are available if checked. Watchdog Counter PDI is only used if
Extended Watchdog feature is selected.
System Time PDI controlled
Distributed Clocks Time Loop Control Unit is controlled by PDI (µController) if selected. EtherCAT
access is not possible. Used for synchronization of secondary EtherCAT busses.
PDI information register
PDI information register 0x014E:0x014F is available. Required if PDI SM/IRQ acknowledge by WRITE
is selected.