BECKHOFF EtherCAT IP Core for Xilinx FPGAs v3.00k - Manual (Page 41)

IP Core Usage
Slave Controller – IP Core for Xilinx FPGAs III-29
- A VHDL package which contains the component declaration of the IP Core
(pk_<design name>_comp.vhd)
Add the component declaration inside this file to any VHDL architecture that instantiates the IP
Core wrapper, or directly include the package.
- A settings file with all the configurations from the IPCore_Config Tool (<design name>.eccnf).
This file can be opened by the IPCore_Config tool for changes and updates.
6. Open Xilinx ISE
7. Add the EtherCAT IP Core sources to your ISE project:
EtherCAT_IPCore.vhd EtherCAT IP Core Library
<design_name>.vhd Wrapper generated by IPCore_Config tool
pk_ECAT_VENDORID.vhd Your specific vendor ID package
8. Add a clock source, a reset controller, and constraints, as well as additional user logic.
9. Implement (synthesize) the design and download it to an FPGA. Use an EtherCAT master to
communicate with the EtherCAT slave. The EtherCAT slave requires an SII EEPROM (or another
non-volatile storage) which contains the EtherCAT Slave Information (ESI) for device
identification.
4.2 EDK designs with EtherCAT IP Core
The EtherCAT IP Core can also be integrated into a System on a Programmable Chip (SOPC) with a
processor inside the FPGA (e.g., Xilinx MicroBlaze processor). The EtherCAT IP Core and the
processor can communicate via a PLB or AXI on-chip bus system.
The Xilinx Environment Development Kit (EDK) is used for building an SOPC including the EtherCAT
IP Core.
1. Create an EDK project using Xilinx EDK.
2. Create a folder called pcores in the EDK project folder (next to system.xmp) if there is not already
one.
3. Start IPCore_Config.exe located in the directory <IPInst_dir>\IPCore_Config
4. Browse to the pcores folder and enter a new design name for your EtherCAT IP Core.
5. Configure the IP Core with a PLB or AXI PDI.
6. Generate IP Core by pressing the Generate button if configuration is complete.
The tool will generate an IP for the Xilinx EDK containing these files:
- <design name>.eccnf contains the configuration
- <design name>_<version> folder tree for the EDK with the following files in it:
- data\<design name>_v2_1_0.mpd is the SOPC IP core Microprocessor Peripheral Definition
- data\<design name>_v2_1_0.pao is the SOPC IP core Peripheral Analyze Order
- hdl\vhdl\<design name>.vhd is the VHDL wrapper for the user configured IP core
- doc\pk_<design name>_comp.vhd is the component declaration package of the IP Core
The tool will also copy some files from the EtherCAT IP installation folder to the folder tree:
- hdl\vhdl\EtherCAT_IPCore.vhd is the EtherCAT IP Core
- hdl\vhdl\pk_ECAT_VENDORID.vhd is your Vendor ID package
- other IP core documentation is copied to the doc folder
The last files can only be found and copied by the IPCore_Config tool if the
ETHERCAT_XIL_INST environment variable is set correctly to point to <IPInst_dir>, otherwise
these files have to be added manually. The IPCore_Config tool gives advice if this happens
7. In Xilinx EDK, rescan the user repositories (menu Project – Rescan User Repositories) after each
update of the EtherCAT IP Core.