BECKHOFF EtherCAT IP Core for Xilinx FPGAs v3.00k - Manual (Page 108)

PDI Description
III-96 Slave Controller – IP Core for Xilinx FPGAs
SOF
DATA Input DATA
t
SOF_to_DATA_setup
t
SOF
t
SOF_to_DATA_hold
Figure 39: Digital Input: Input data sampled at SOF, I/O can be read in the same frame
LATCH_IN
DATA Input DATA
t DATA_hold t DATA_setup
t
LATCH_IN
t
Input_event_delay
Figure 40: Digital Input: Input data sampled with LATCH_IN
SYNC0/1
DATA Input DATA
t
DATA_hold
t
DATA _set up
t
Input_event_delay
Figure 41: Digital Input: Input data sampled with SYNC0/1