BECKHOFF EtherCAT IP Core for Xilinx FPGAs v3.00k - Manual (Page 68)

FPGA Resource Consumption
III-56 Slave Controller – IP Core for Xilinx FPGAs
7 FPGA Resource Consumption
The resource consumption figures shown in this chapter reflect results of example synthesis runs and
can only be used for rough resource estimations. The figures are subject to quite large variations
depending on design tools and version, FPGA type, constraints (e.g., area vs. speed), total FPGA
utilization (design tools typically stop optimization if the timing goal is reached), etc. No extra effort
was undertaken to achieve optimum results, i.e. by sophisticated constraining and design flow setting.
For accurate resource consumption figures, please use the evaluation license of the EtherCAT IP
Core and synthesize your individual configuration for the desired FPGA.
The figures of the following table do not imply that the individual features are operational in the
selected FPGA (i.e., that the resources are sufficient or that timing closure is achievable). The
synthesis runs where performed without timing constraints, without location constraints, and without
bitstream generation.
The EtherCAT IP core resource consumption overview figures are based on EtherCAT IP Core for
Xilinx FPGAs Version 3.00c, Xilinx ISE 14.5, and Xilinx Spartan-6 devices. One Spartan-6 slice
contains 4 lookup-tables (LUT6) and 4 flip-flops. The registers and logic LUT figures are subject to
variation as a result of optimization. Slice figures are not given any more since their variation is
extremely high.