BECKHOFF EtherCAT IP Core for Xilinx FPGAs v3.00k - Manual (Page 113)

PDI Description
Slave Controller – IP Core for Xilinx FPGAs III-101
10.2.8.1 Read Wait State
Between the last address phase byte and the first data byte of a read access, the SPI master has to
wait for the SPI slave to fetch the read data internally. Subsequent read data bytes are prefetched
automatically, so no further wait states are necessary.
The SPI master can choose between these possibilities:

The SPI master may either wait for the specified worst case internal read time t
read
after the last
address/command byte and before the first clock cycle of the data phase.

The SPI master inserts one Wait State byte after the last address/command byte. The Wait State
byte must have a value of 0xFF transferred on SPI_DI.
10.2.8.2 Read Termination
The SPI_DI signal (MOSI) is used for termination of the read access by the SPI master. For the last
data byte, the SPI master has to set SPI_DI to high (Read Termination byte = 0xFF), so the slave will
not prefetch the next read data internally. If SPI_DI is low during a data byte transfer, at least one
more byte will be read by the master afterwards.
10.2.9 SPI access errors and SPI status flag
The following reasons for SPI access errors are detected by the SPI slave:

The number of clock cycles recognized while SPI_SEL is asserted is not a multiple of 8
(incomplete bytes were transferred).

For a read access, a clock cycle occurred while the slave was busy fetching the first data byte.

For a read access, the data phase was not terminated by setting SPI_DI to high for the last byte.

For a read access, additional bytes were read after termination of the access.
A wrong SPI access will have these consequences:

Registers will not accept write data (nevertheless, RAM will be written).

Special functions are not executed (e.g., SyncManager buffer switching).

The PDI error counter 0x030D will be incremented.

A status flag will indicate the error until the next access (not for SPI mode 0/2 with normal data out
sample)
A status flag, which indicates if the last access had an error, is available in any mode except for SPI
mode 0/2 with normal data out sample. The status flag is presented on SPI_DO (MISO) after the slave
is selected (SPI_SEL) and until the first clock cycle occurs. So the status can be read either between
two accesses by assertion of SPI_SEL without clocking, or at the beginning of an access just before
the first clock cycle. The status flag will be high for a good access, and low for a wrong access.
The reason of the access error can be read in the PDI error code register 0x030E.