BECKHOFF EtherCAT IP Core for Xilinx FPGAs v3.00k - Manual (Page 140)

Electrical Specifications
III-128 Slave Controller – IP Core for Xilinx FPGAs
13 Electrical Specifications
Table 68: AC Characteristics
Symbol Parameter Min Typ Max Units
f
CLK25
Clock source (CLK25) with initial
accuracy 25 MHz ± 25 ppm
Table 69: Forwarding Delays
Symbol Parameter Min Average Max Units
PRELIMINARY TIMING
t
Diff
Average difference processing
delay minus forwarding delay
(without RX FIFO jitter)
40 ns
t
MM
MII port to MII port delay:
a) Through ECAT Processing Unit
(processing)
b) Alongside ECAT Processing Unit
(forwarding)
Conditions: FIFO size 7, no TX Shift
compensation or manual TX Shift
configuration with
MII_TX_SHIFT = 00
a) 300+x 17
b) 260+x 17
a) 320+x 17
b) 280+x 17
a) 340+x 17
b) 300+x 17
ns
NOTE: Average timings are used for DC calculations.
17 EtherCAT IP Core: time depends on synthesis results