BECKHOFF EtherCAT IP Core for Xilinx FPGAs v3.00k - Manual (Page 63)

Example Designs
Slave Controller – IP Core for Xilinx FPGAs III-51
6.1.4 SII EEPROM
Use this ESI for the SII EEPROM:
Beckhoff Automation GmbH (Evaluation)/
IP Core example designs ET1815 (Xilinx)/
ET1815 IP Core Avnet LX150T DIGI
6.1.5 Downloadable configuration file
An already synthesized time limited configuration file
LX150T_DIGI_Demo_V3_00c_time_limited.bit
based on this example design can be found in the
<IPInst_dir>\example_designs\LX150T_DIGI\
folder. After expiration of about 1 hour the design quits its operation. These files must only be used for
evaluation purposes, any distribution is not allowed.