Altera RapidIO II MegaCore Function - Manual (Page 10)

1–2 Chapter 1: About The RapidIO II MegaCore Function
Features
RapidIO II MegaCore Function August 2014 Altera Corporation
User Guide
New Features in the RapidIO II IP Core v14.0 and v14.0 Arria 10 Edition
Releases
The RapidIO II IP core v14.0 Arria 10 Edition adds the following new feature:
■ Support for Arria 10 devices
For details about changes to the IP core, refer to “Document Revision History” on
page Info–1 . For an overview, refer to the RapidIO II IP core chapter in the Altera
MegaCore Library Release Notes . IP core variations that target an Arria 10 device have
additional interfaces and design requirements.
f For information about the new Altera IP design flow in the Quartus II software v14.0
and v14.0 Arria 10 Edition, which impacts all Altera IP cores, refer to the
“Introduction to Altera IP Cores” section in the “Managing Quartus II Projects”
chapter in
Volume 1: Design and Synthesis of the Quartus II Handbook and to Introduction
to Altera IP Cores .
The RapidIO II IP core v13.0 and v13.1 do not add any new features.
RapidIO II IP Core Features
The RapidIO II IP core has the following features:
■ Compliant with the RapidIO Trade Association RapidIO Interconnect Specification,
Revision 2.2, June 2011, available from the RapidIO Trade Association website at
www.rapidio.org
■ Supports 8-bit or 16-bit device IDs
■ Supports incoming and outgoing multi-cast events
■ Provides a 128-bit wide Avalon Streaming (Avalon-ST) pass-through interface for
fully integrated implementation of custom user logic