Altera RapidIO II MegaCore Function - Manual (Page 19)

August 2014 Altera Corporation RapidIO II MegaCore Function
User Guide
2. Getting Started
You can customize the RapidIO II IP core to support a wide variety of applications.
When you generate the IP core you can choose whether or not to generate a
simulation model. If you generate a simulation model, Altera provides a Verilog
testbench customized for your IP core variation. If you specify a VHDL simulation
model, you must use a mixed-language simulator to run the testbench, or create your
own VHDL-only simulation environment.
Customizing and Generating IP Cores
You can customize IP cores to support a wide variety of applications. The Quartus II
IP Catalog displays IP cores available for the current target device. The parameter
editor guides you to set parameter values for optional ports, features, and output files.
To customize and generate a custom IP core variation, follow these steps:
1. In the IP Catalog (Tools > IP Catalog), locate and double-click the name of the IP
core to customize. The parameter editor appears.
2. Specify a top-level name for your custom IP variation. This name identifies the IP
core variation files in your project. If prompted, also specify the target Altera
device family and output file HDL preference. Click OK.
3. Specify the desired parameters, output, and options for your IP core variation:
■ Optionally select preset parameter values. Presets specify all initial parameter
values for specific applications (where provided).
■ Specify parameters defining the IP core functionality, port configuration, and
device-specific features.
■ Specify options for generation of a timing netlist, simulation model, testbench,
or example design (where applicable).
■ Specify options for processing the IP core files in other EDA tools.
4. Click Finish or Generate to generate synthesis and other optional files matching
your IP variation specifications. The parameter editor generates the top-level .qip
or .qsys IP variation file and HDL files for synthesis and simulation. Some IP cores
also simultaneously generate a testbench or example design for hardware testing.
When you generate the IP variation with a Quartus II project open, the parameter
editor automatically adds the IP variation to the project. Alternatively, click Project >
Add/Remove Files in Project
to manually add a top-level .qip or .qsys IP variation
file to a Quartus II project. To fully integrate the IP into the design, make appropriate
pin assignments to connect ports. You can define a virtual pin to avoid making
specific pin assignments to top-level signals.