Altera RapidIO II MegaCore Function - Manual (Page 213)

August 2014 Altera Corporation RapidIO II MegaCore Function
User Guide
Additional Information
This chapter provides additional information about the document and Altera.
Document Revision History
The following table shows the revision history for this user guide.
Date Version Changes
August 2014
14.0
Arria 10
Edition
■ Added support for Arria 10 devices:
■ New parameter Enable transceiver dynamic reconfiguration allows you to hide or
make visible the Arria 10 Native PHY IP core dynamic reconfiguration interface, an
Avalon-MM interface for programming the hard registers in the Arria 10 transceiver.
Information added in
Chapter 2, Getting Started , “Clocking and Reset Structure” on
page 4–3 , Chapter 3, Parameter Settings , and Chapter 5, Signals .
■ New requirement to include TX PLL IP core in the design. New individual transceiver
channel clock signals added to RapidIO II IP core to connect to an ATX PLL to support
PLL sharing across the transceiver block. Information added in
Chapter 2, Getting
Started , “Clocking and Reset Structure” on page 4–3 and Chapter 5, Signals .
■ Removed pll_locked and pll_powerdown signals from RapidIO II IP core that
targets an Arria 10 device. Information added in
Table 5–7 on page 5–5 .
■ Updated Appendix A, Initialization Sequence to clarify that it addresses initialization of
RapidIO II IP cores rather than RapidIO IP cores. The initialization sequence is
identical for the two IP cores.