Altera RapidIO II MegaCore Function - Manual (Page 79)

Chapter 4: Functional Description 4–37
Logical Layer Interfaces
August 2014 Altera Corporation RapidIO II MegaCore Function
User Guide
Port-Write Transmission
To send a RapidIO MAINTENANCE port-write packet to a remote device, you must
program the transmit port-write control and data registers. The Tx Port Write
Control
register is described in Table 6–45 on page 6–36 and the Tx Port Write Buffer
is described in Table 6–47 on page 6–37 . You access these registers using the Register
Access Avalon-MM slave interface. You must program the values for the following
header fields in the corresponding fields in the Tx Port Write Control register:
■ DESTINATION_ID
■ priority
■ wrsize
The RapidIO II IP core assigns the following values to the fields of the MAINTENANCE
port-write
packet:
■ Assigns ftype the value of 4'b1000
■ Assigns ttype the value of 4'b0100
■ Calculates the values for the wdptr and wrsize fields of the transmitted packet
from the size of the payload to be sent, as defined by the size field of the Tx Port
Write
Control register
■ Assigns the value of 0 to the Reserved source_tid and config_offset fields
The IP core creates the packet’s payload from the contents of the Tx Port Write Buffer
sequence of registers starting at register address 0x10210. This buffer can store a
maximum of 64 bytes. The IP core starts the packet composition and transmission
process after you set the PACKET_READY bit in the Tx Port Write Control register. The
RapidIO II IP core composes the Maintenance port-write packet and transmits it on
the RapidIO link.
Port-Write Reception
When the RapidIO II IP core Maintenance module receives a MAINTENANCE port-write
request packet (ftype has the value of 4’b1000 and ttype has the value of 4’b0100)
from the Transport layer, it extracts information from the packet header and uses the
information to write to registers Rx Port Write Control (
Table 6–48 on page 6–37 )
through Rx Port Write Buffer ( Table 6–50 on page 6–37 ). The Maintenance module
extracts information from the following fields:
■ wrsize — the values in the wrsize and wdptr packet fields determine the value of
the PAYLOAD_SIZE field in the Rx Port Write Status register ( Table 6–49 on
page 6–37 ).
■ wdptr — the values in the wrsize and wdptr packet fields determine the value of
the PAYLOAD_SIZE field in the Rx Port Write Status register ( Table 6–49 on
page 6–37 ).
■ payload — the Maintenance module copies the value of the payload packet field to
the Rx Port Write Buffer starting at register address 0x10260. This buffer holds a
maximum of 64 bytes.
While the IP core is writing the payload to the buffer, it holds the PORT_WRITE_BUSY bit
of the Rx Port Write Status register asserted. After the payload is completely written
to the buffer, if you have set the RX_PACKET_STORED bit of the Maintenance Interrupt
Enable
register ( Table 6–40 on page 6–35 ), the IP core asserts the interrupt signal