Altera RapidIO II MegaCore Function - Manual (Page 197)

Chapter 7: Testbench 7–3
Testbench Sequence
August 2014 Altera Corporation RapidIO II MegaCore Function
User Guide
Figure 7–1 illustrates the system specified in Verilog HDL. The testbench generates
and checks activity across the Avalon-MM interfaces by running tasks that are defined
in the BFMs.
The file tb_rio.v implements the code that performs the test transactions. The code
performs a reset and initialization sequence necessary for the DUT and sister_rio IP
cores to establish a link and exchange packets.
Testbench Sequence
The RapidIO II IP core testbench resets the DUT and the sister_rio module and
initiates a sequence of transactions on each Avalon-MM and Avalon-ST interface that
is relevant to this RapidIO II IP core variation. The following sections describe the
reset and transaction sequences.
Reset, Initialization, and Configuration
The clocks that drive the testbench are defined and generated in the tb_rio.sv file.
1 Refer to tb_rio.sv for the exact frequencies used for each of the clocks. The frequencies
depend on the configuration of the variation.
The reset sequence is simple—the main reset signal for the DUT and the sister_rio IP
core, rst_n, is driven low at the beginning of the simulation, is kept low for 200 ns,
and is then deasserted. The testbench also includes two Altera Transceiver PHY Reset
Controller IP cores, connected to the DUT and sister IP core. While rst_n is asserted,
the reset input signal to the Transceiver PHY Reset Controller IP core is also asserted.
After rst_n is deasserted, the testbench waits until both the DUT and the sister_rio
modules have driven their port_initialized
output signals high. These signal
transitions indicate that both IP cores have completed their initialization sequence.
The testbench then waits an additional 5000 ns, to allow time for a potential reset
link-request control symbol exchange between the DUT and the sister_rio module.
The testbench again waits until both the DUT and the sister_rio modules have driven
their port_initialized output signals high. Following the 5000 ns wait, the testbench
checks that the port initialization process completed successfully by reading the Error
and Status CSR
to confirm the expected values of the PORT_OK and PORT_UNINIT
register bits. These register fields indicate that the link is established and the Physical
layer is ready to exchange traffic.