Altera RapidIO II MegaCore Function - Manual (Page 78)

4–36 Chapter 4: Functional Description
Logical Layer Interfaces
RapidIO II MegaCore Function August 2014 Altera Corporation
User Guide
■ For a MAINTENANCE write, converts the received request packet to an Avalon write
transfer and presents it across the Maintenance Avalon-MM master interface.
■ For each Avalon read request the IP core presents on the Maintenance Avalon-MM
master interface, the Maintenance module accepts the data response, generates a
Type 8 Response packet, and presents the response packet to the Transport layer
for transmission on the RapidIO link.
f
Refer to Avalon Interface Specifications for details on the supported transfers.
The Maintenance module only supports single 32-bit word transfers, that is, rdsize
and wrsize = 4’b1000. If the RapidIO II IP core receives a MAINTENANCE request on the
RapidIO link with a different value in this field, the IP core sends an error response
packet on the RapidIO link, and no transfer occurs.
The RapidIO II IP core uses the wdptr and config_offset values in the incoming
RapidIO request packet to generate the Avalon-MM address in the transaction it
presents on the Maintenance module master interface, using the following formula:
usr_mnt_address = {8’h00, config_offset, ~wdptr, 2'b00}
The IP core presents the data in the RapidIO transaction payload field on the
usr_mnt_writedata[31:0]
bus.
Handling Port-Write Transactions
The RapidIO II IP core supports RapidIO MAINTENANCE port-write transactions.
However, these transactions do not appear on the Maintenance Avalon-MM interface.
User logic controls the processing of port-write transactions by programming the
registers that are described in the following sections:
■ “Transmit Port-Write Registers” on page 6–36
■ “Receive Port-Write Registers” on page 6–37
Your system controls the transmission of port-write transactions on the RapidIO link
by programming RapidIO II IP core transmit port-write registers using the Register
Access interface. When the RapidIO II IP core receives a MAINTENANCE port-write
request packet on the RapidIO link, it processes the transaction according to the
values you program in the receive port-write registers, and if you have enabled this
interrupt signal, asserts the mnt_mnt_s_irq signal to inform the system that the IP core
has received a port-write transaction.
IP Core Actions
The port-write processor in the Maintenance module performs the following tasks:
■ Composes the RapidIO MAINTENANCE port-write request packet.
■ Presents the port-write request packet to the Transport layer for transmission.
■ Processes port-write request packets received across the RapidIO link from a
remote device.
■ Alerts the user of a received port-write using the mnt_mnt_s_irq signal.