Altera RapidIO II MegaCore Function - Manual (Page 95)

Chapter 4: Functional Description 4–53
Logical Layer Interfaces
August 2014 Altera Corporation RapidIO II MegaCore Function
User Guide
Pass-Through Interface Receive Side Data Signals
Table 4–27 lists the Avalon-ST pass-through interface receive side payload data
signals. The application should sample payload data only when both
gen_rx_pd_ready
and gen_rx_pd_valid are asserted.
Pass-Through Interface Receive Side Header Signals
Table 4–28 lists the Avalon-ST pass-through interface receive side header signals. The
application should sample header data only when both gen_rx_hd_ready and
gen_rx_hd_valid
are asserted.
Table 4–27. Avalon-ST Pass-Through Interface Receive Side (Avalon-ST Source) Data Signals
Signal Name Type Function
gen_rx_pd_ready Input
Indicates to the IP core that the user’s custom logic is ready to receive data on
the current cycle. Asserted by the sink to mark ready cycles, which are cycles in
which transfers can occur. If ready is asserted on cycle N, the cycle
(N+READY_LATENCY) is a ready cycle. The RapidIO II IP core is designed for
READY_LATENCY
equal to 0.
gen_rx_pd_valid Output
Used to qualify all the other output signals of the receive side pass-through
interface. On every rising edge of the clock during which gen_rx_pd_valid is
high, gen_rx_pd_data can be sampled.
(1)
gen_rx_pd_startofpacket Output Marks the active cycle containing the start of the packet. (1)
gen_rx_pd_endofpacket Output Marks the active cycle containing the end of the packet. (1)
gen_rx_pd_data[127:0] Output A 128-bit wide data bus for data payload. (1)
gen_rx_pd_empty[3:0] Output
This bus identifies the number of empty two-byte segments on the 128-bit wide
gen_rx_pd_data
bus on the final data transfer of the packet, which occurs
during the clock cycle when gen_tx_endofpacket is asserted. This signal is 4
bits wide.
(1)
Note to Table 4–27 :
(1) gen_rx_pd_valid qualifies all the other output signals of the transmit side of the Avalon-ST pass-through interface.
Table 4–28. Avalon-ST Pass-Through Interface Receive Side (Avalon-ST Source) Header Signals
Signal Name Type Function
gen_rx_hd_ready Input
Indicates to the IP core that the user’s custom logic is ready to receive packet
header bits on the current clock cycle. Asserted by the sink to mark ready cycles,
which are cycles in which transfers can occur. If ready is asserted on cycle N, the
cycle (N+READY_LATENCY) is a ready cycle. The RapidIO II IP core is designed
for READY_LATENCY equal to 0.
gen_rx_hd_valid Output
Used to qualify the receive side pass-through interface output header bus. On
every rising edge of the clock during which gen_rx_hd_valid is high,
gen_rx_hd_data
can be sampled.
gen_rx_hd_data[114:0] Output
A 115-bit wide bus for packet header bits. Data on this bus is valid only when
gen_rx_hd_valid
is high.