Altera RapidIO II MegaCore Function - Manual (Page 26)

2–8 Chapter 2: Getting Started
Integrating Your IP Core in Your Design
RapidIO II MegaCore Function August 2014 Altera Corporation
User Guide
Transceiver Settings
Altera recommends that you maintain the default Native PHY IP core settings
generated for the RapidIO II IP core. If you edit the existing Native PHY IP core, the
regenerated Native PHY IP core does not instantiate correctly in the top-level
RapidIO II IP core. If you must modify transceiver settings, perform the modifications
by editing the project Quartus Settings File (.qsf).
Adding Transceiver Analog Settings for Arria V GZ and Stratix V Variations
In general, Altera recommends that you maintain the default transceiver settings
specified by the RapidIO II IP core. However, Arria V GZ or Stratix V variations
require that you specify some analog transceiver settings.
After you generate your RapidIO II IP core in a Quartus II project that targets an
Arria V GZ or Stratix V device, perform the following steps:
1. In the Quartus II software, on the Assignments tab, click Assignment Editor.
2. In the Assignment Editor, in the Assignment Name column, double click
<<new>> and select Transceiver Analog Settings Protocol.
3. In the To column, type the name of the transceiver serial data input node in your
IP core variation. This name is the variation-specific version of the rd signal.
4. In the Value column, click and select SRIO.
5. Repeat steps 2 to 4 to create an additional assignment, with the following
substitution:
In step 3 , instead of typing the name of the transceiver serial data input node, type
the name of the transceiver serial data output put node. This name is the
variation-specific version of the td signal.
External Transceiver PLL
RapidIO II IP cores that target an Arria 10 device require an external TX transceiver
PLL to compile and to function correctly in hardware. You must instantiate and
connect this IP core to the RapidIO II IP core.
You can create an external transceiver PLL from the IP Catalog. Select the ATX PLL IP
core or the fPLL IP core. In the ATX TX PLL parameter editor, set the following
parameter values:
■ Set PLL output frequency to one half the value you select for the Maximum baud
rate
parameter in the RapidIO II parameter editor. The transceiver performs dual
edge clocking, using both the rising and falling edges of the input clock from the
PLL. Therefore, this PLL output frequency setting supports the customer-selected
maximum data rate on the RapidIO link.
■ Set PLL reference clock frequency to the value you select for the Reference clock
frequency
parameter in the RapidIO II parameter editor.
■ Turn on Include Master Clock Generation Block.
■ Turn on Enable bonding clock output ports.
■ Set PMA interface width to 20.