Altera RapidIO II MegaCore Function - Manual (Page 77)

Chapter 4: Functional Description 4–35
Logical Layer Interfaces
August 2014 Altera Corporation RapidIO II MegaCore Function
User Guide
■ hop_count
You can disable an address translation window that is available in your configuration.
The RapidIO II IP core includes one set of Tx Maintenance Mapping Window registers
for each translation window. The following registers define address translation
window n:
■ A base register: Tx Maintenance Mapping Window n Base ( Table 6–41 on page 6–35 )
■ A mask register: Tx Maintenance Mapping Window n Mask ( Table 6–42 )
■ An offset register: Tx Maintenance Mapping Window n Offset ( Table 6–43 )
■ A control register: Tx Maintenance Mapping Window n Control ( Table 6–44 )
To enable a window, set the window enable (WEN) bit of the window’s Tx Maintenance
Window
n Mask register ( Table 6–42 on page 6–35 ) to the value of 1. To disable it, set the
WEN bit to the value of zero.
For each defined and enabled window, the RapidIO II IP core masks out the
Avalon-MM address's least significant bits with the window mask and compares the
resulting address to the window base. If the address matches multiple windows, the
IP core uses the lowest number matching window.
After determining the appropriate matching window, the RapidIO II IP core creates
the 21-bit config_offset value in the converted MAINTENANCE transaction based on the
following equation:
If (mnt_s_address[23:1] & mask[25:3]) == base[25:3]
then config_offset = (offset[23:3] & mask[23:3])|
(mnt_s_address[21:1] & ~mask[23:3])
where:
■ mnt_s_address[23:0] is the Avalon-MM slave interface address signal, which
holds bits [25:2] of the 26-bit byte address
■ mask[31:0] is the mask register
■ base[31:0] is the base address register
■ offset[23:0] is the OFFSET field of the window offset register
Responding to MAINTENANCE Read and Write Requests
To respond to a MAINTENANCE read or write request packet it receives on the RapidIO
link, the RapidIO II IP core sends a read or write request to the Maintenance module
master interface. Refer to
“Maintenance Interface Transaction Examples” on
page 4–38 for examples of how the RapidIO MAINTENANCE request appears on the
Maintenance module master port and the expected format of your system response.
IP Core Actions
In response to incoming MAINTENANCE requests on the RapidIO link that do not target
the RapidIO II IP core internal register set, the RapidIO II IP core Maintenance
module generates Avalon-MM requests on the Maintenance module master interface,
by performing the following tasks:
■ For a MAINTENANCE read, converts the received request packet to an Avalon read
request and presents it across the Maintenance Avalon-MM master interface.