Altera RapidIO II MegaCore Function - Manual (Page 131)

Chapter 5: Signals 5–7
Physical Layer Signals
August 2014 Altera Corporation RapidIO II MegaCore Function
User Guide
reconfig_address_ch1[9:0] Input
Arria 10 dynamic reconfiguration slave address bus for the
transceiver channel configured for RapidIO lane 1. The address is a
word address, not a byte address.
This signal is available only in 2x and 4x variations.
reconfig_writedata_ch1[31:0] Input
Arria 10 dynamic reconfiguration slave write data bus for the
transceiver channel configured for RapidIO lane 1. This signal is
available only in 2x and 4x variations.
reconfig_readdata_ch1[31:0] Output
Arria 10 dynamic reconfiguration slave read data bus for the
transceiver channel configured for RapidIO lane 1. This signal is
available only in 2x and 4x variations.
reconfig_clk_ch2 Input
Arria 10 dynamic reconfiguration interface clock for the transceiver
channel configured for RapidIO lane 2. This signal is available only in
4x variations.
reconfig_reset_ch2 Input
Arria 10 dynamic reconfiguration interface reset for the transceiver
channel configured for RapidIO lane 2. This signal is available only in
4x variations.
reconfig_waitrequest_ch2 Output
Arria 10 dynamic reconfiguration slave wait request for the
transceiver channel configured for RapidIO lane 2. The RapidIO II IP
core uses this signal to stall the requestor on the interconnect.
This signal is available only in 4x variations.
reconfig_read_ch2 Input
Arria 10 dynamic reconfiguration slave read request for the
transceiver channel configured for RapidIO lane 2. This signal is
available only in 4x variations.
reconfig_write_ch2 Input
Arria 10 dynamic reconfiguration slave write request for the
transceiver channel configured for RapidIO lane 2. This signal is
available only in 4x variations.
reconfig_address_ch2[9:0] Input
Arria 10 dynamic reconfiguration slave address bus for the
transceiver channel configured for RapidIO lane 2. The address is a
word address, not a byte address.
This signal is available only in 4x variations.
reconfig_writedata_ch2[31:0] Input
Arria 10 dynamic reconfiguration slave write data bus for the
transceiver channel configured for RapidIO lane 2. This signal is
available only in 4x variations.
reconfig_readdata_ch2[31:0] Output
Arria 10 dynamic reconfiguration slave read data bus for the
transceiver channel configured for RapidIO lane 2. This signal is
available only in 4x variations.
reconfig_clk_ch3 Input
Arria 10 dynamic reconfiguration interface clock for the transceiver
channel configured for RapidIO lane 3. This signal is available only in
4x variations.
reconfig_reset_ch3 Input
Arria 10 dynamic reconfiguration interface reset for the transceiver
channel configured for RapidIO lane 3. This signal is available only in
4x variations.
reconfig_waitrequest_ch3 Output
Arria 10 dynamic reconfiguration slave wait request for the
transceiver channel configured for RapidIO lane 3. The RapidIO II IP
core uses this signal to stall the requestor on the interconnect.
This signal is available only in 4x variations.
Table 5–8. Arria 10 Transceiver Dynamic Reconfiguration Avalon-MM Interface Signals (Part 2 of 3) (Part 2 of 3)
Signal Direction Description