Installation and licensing, Opencore plus evaluation, Installation and licensing –9 – Altera RapidIO II MegaCore Function User Manual

Page 17: Opencore plus evaluation –9

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Chapter 1: About The RapidIO II MegaCore Function

1–9

Installation and Licensing

August 2014

Altera Corporation

RapidIO II MegaCore Function

User Guide

Altera verifies that the current version of the Quartus II software compiles the
previous version of each IP core. Any exceptions to this verification are reported in the

MegaCore IP Library Release Notes

and in the

Altera RapidIO II IP core errata

. Altera

does not verify compilation with IP core versions older than the previous release.

Installation and Licensing

The RapidIO II IP core is part of the Altera MegaCore IP Library, which is distributed
with the Quartus II software and downloadable from the Altera website,

www.altera.com

.

Figure 1–2

shows the directory structure after you install the RapidIO II IP core,

where <path> is the installation directory. The default installation directory on
Windows is C:\altera\<version number>; on Linux it is /opt/altera<version number>.

You can use Altera’s free OpenCore Plus evaluation feature to evaluate the IP core in
simulation and in hardware before you purchase a license. You must purchase a
license for the IP core only when you are satisfied with its functionality and
performance, and you want to take your design to production.

After you purchase a license for the RapidIO II IP core, you can request a license file
from the Altera website at

www.altera.com/licensing

and install it on your computer.

When you request a license file, Altera emails you a license.dat file. If you do not have
internet access, contact your local Altera representative.

OpenCore Plus Evaluation

With the Altera free OpenCore Plus evaluation feature, you can perform the following
actions:

Simulate the behavior of a megafunction (Altera IP core or AMPP

SM

megafunction) in your system using the Quartus II software and Altera-supported
VHDL and Verilog HDL simulators.

Verify the functionality of your design and evaluate its size and speed quickly and
easily.

Generate time-limited device programming files for designs that include IP cores.

Program a device and verify your design in hardware.

Figure 1–2. Directory Structure

<path>

common
Contains shared components

altera_rapidio2
Contains the RapidIO II MegaCore function files

Installation directory

ip
Contains the Altera MegaCore IP Library and third-party IP cores

altera
Contains the Altera MegaCore IP Library

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