Altera RapidIO II MegaCore Function - Manual (Page 12)

1–4 Chapter 1: About The RapidIO II MegaCore Function
Device Family Support
RapidIO II MegaCore Function August 2014 Altera Corporation
User Guide
■ Input/Output Avalon ® Memory-Mapped (Avalon-MM) master and slave
Logical layer modules with 128-bit wide datapath and burst support
■ Doorbell module supporting 16 outstanding DOORBELL packets with time-out
mechanism
■ Optional preservation of transaction order between outgoing DOORBELL
messages and I/O write requests
■ Registers and interrupt indicate NWRITE_R transaction completion
■ Preservation of transaction order between outgoing I/O read requests and I/O
write requests from Avalon-MM interfaces
■ Cycle-accurate simulation models for use in Altera-supported VHDL and Verilog
HDL simulators
■ IEEE-encrypted HDL simulation models for improved simulation efficiency
■ Support for OpenCore Plus evaluation
Supported Transactions
The RapidIO II IP core supports the following RapidIO transactions:
■ NREAD request and response
■ NWRITE request
■ NWRITE_R request and response
■ SWRITE request
■ MAINTENANCE read request and response
■ MAINTENANCE write request and response
■ MAINTENANCE port-write request
■ DOORBELL request and response
Device Family Support
Table 1–1 defines the device support levels for Altera IP cores.
Table 1–1. Altera IP Core Device Support Levels
Preliminary support—The IP core is verified with preliminary timing models for this device family.
The IP core meets all functional requirements, but might still be undergoing timing analysis for the
device family. It can be used in production designs with caution.
Final support—The IP core is verified with final timing models for this device family. The IP core
meets all functional and timing requirements for the device family and can be used in production
designs.