Altera RapidIO II MegaCore Function - Manual (Page 89)

Chapter 4: Functional Description 4–47
Logical Layer Interfaces
August 2014 Altera Corporation RapidIO II MegaCore Function
User Guide
The corresponding interrupt status bit is set each time a valid response packet is
received, and resets itself when the Tx Completion FIFO is empty. Software optionally
can clear the interrupt status bit by writing a 1 to this specific bit location of the
Doorbell
Interrupt Status register ( Table 6–93 ).
Upon detecting the interrupt, software can fetch the completed message and
determine its status by reading the Tx Doorbell Completion (
Table 6–89 ) register and
Tx Doorbell Completion Status register ( Table 6–90 ), respectively.
An outbound DOORBELL message is assigned a time-out value based on the VALUE field
of the Port Response Time-Out Control register (
Table 6–8 on page 6–8 ) and a
free-running counter. When the counter reaches the time-out value, if the DOORBELL
transaction has not yet received a response, the transaction times out. Refer to
Table 6–8 for information about how the time-out value is calculated.
An outbound message that times out before its response is received is treated in the
same manner as an outbound message that receives an error response: if the TX_CPL
field of the Doorbell Interrupt Enable register (
Table 6–92 on page 6–55 ) is set, the
Doorbell module generates an interrupt by asserting the drbell_s_irq signal, and
setting the ERROR_CODE field in the Tx Doorbell Completion Status register
(
Table 6–90 ) to indicate the error.
If the interrupt is not enabled, the Avalon-MM master must periodically poll the Tx
Doorbell
Completion Status register to check for available completed messages
before retrieving them from the Tx Completion FIFO.
DOORBELL request packets for which RETRY responses are received are resent by
hardware automatically. No retry limit is imposed on outbound DOORBELL messages.
Receiving a Doorbell Message
When the Doorbell module receives a DOORBELL request packet from the Transport
layer module, the module stores the request in an internal buffer and generates an
interrupt on the DOORBELL Avalon-MM slave interface—asserts the
drbell_s_irq
signal—if this interrupt is enabled.
The corresponding interrupt status bit is set every time a DOORBELL request packet is
received and resets itself when the Rx FIFO is empty. Software can clear the interrupt
status bit by writing a 1 to this specific bit location of the Doorbell Interrupt Status
register (
Table 6–93 ).
The RapidIO II IP core generates an interrupt when it receives a valid response packet
and when it receives a request packet. Therefore, when user logic receives an interrupt
(the
drbell_s_irq signal is asserted), you must check the Doorbell Interrupt Status
register to determine the type of event that triggered the interrupt.
If the interrupt is not enabled, user logic must periodically poll the Rx Doorbell
Status
register ( Table 6–85 ) to check the number of available messages before
retrieving them from the Rx doorbell buffer.
The Doorbell module generates and sends appropriate Type 13 response packets for
all the DOORBELL messages it receives. The module generates a response with the
following status, depending on its ability to process the message:
■ With DONE status if the received DOORBELL packet can be processed immediately
■ With RETRY status to defer processing the received message when the internal
hardware is busy, for example when the Rx doorbell buffer is full