Altera RapidIO II MegaCore Function - Manual (Page 44)

4–2 Chapter 4: Functional Description
Interfaces
RapidIO II MegaCore Function August 2014 Altera Corporation
User Guide
In variations of the RapidIO II IP core that have 128-bit wide Avalon-MM interfaces,
the least significant half of the Avalon-MM 128-bit word corresponds to the 8-byte
double word at RapidIO address N, and the most significant half of the Avalon-MM
128-bit word corresponds to the 8-byte double word at RapidIO address N+8. If two
8-byte double words appear in the RapidIO packet in the order dw0, followed by
dw1, they appear on the 128-bit Avalon-MM interface as the 128-bit word {dw1, dw0}.
Table 4–1 shows the ordering of the bytes in each 8-byte double word. Table 4–2
shows the ordering of the 8-byte double words in each 128-bit Avalon-MM word.
Avalon Streaming (Avalon-ST) Interface
The Avalon-ST interface provides a standard, flexible, and modular protocol for data
transfers from a source interface to a sink interface. The Avalon-ST interface protocol
allows you to easily connect components together by supporting a direct connection
to the Transport layer. The Avalon-ST interface is 128 bits wide. This interface is
available to create custom Logical layer functions like message passing.
For more information about how to use the RapidIO II IP core Avalon-ST interface,
refer to the
“Avalon-ST Pass-Through Interface” on page 4–48 .
f For more information about the Avalon-ST interface, refer to Avalon Interface
Specifications .
RapidIO Interface
The RapidIO interface complies with revision 2.2 of the RapidIO ® serial interface
standard described in the RapidIO Trade Association specifications. The protocol is
divided into a three-layer hierarchy: Physical layer, Transport layer, and Logical layer.
Avalon-
MM
Protocol
(Little
Endian)
Byte7[7:0] Byte6[7:0] Byte5[7:0] Byte4[7:0] Byte3[7:0] Byte2[7:0] Byte1[7:0] Byte0[7:0]
Address=
N+7
Address=
N+6
Address=
N+5
Address=
N+4
Address=
N+3
Address=
N+2
Address=
N+1
Address=
N
32-Bit Word[31:0] 32-Bit Word[31:0]
Avalon-MM Byte Address = N+4 Avalon-MM Byte Address = N
64-bit Double Word0[63:0]
Avalon-MM Byte Address = N
Table 4–1. Byte Ordering (Part 2 of 2)
Byte
Lane
(Binary)
1000_0000 0100_0000 0010_0000 0001_0000 0000_1000 0000_0100 0000_0010 0000_0001
Table 4–2. Double-Word Ordering in a 128-Bit Avalon-MM Interface
Protocol
RapidIO Protocol
(Big Endian)
Second Transmitted Double Word[0:63] First Transmitted Double Word[0:63] (1)
RapidIO Byte Address N + 8 RapidIO Byte Address N = {29'hn, 3'b000}
Avalon-MM Protocol
(Little Endian)
64-Bit Double Word[63:0] 64-Bit Double Word[63:0]
Avalon-MM Byte Address = N+8 Avalon-MM Byte Address = N
Note to Table 4–2 :
(1) Bit 0 of the RapidIO double word is transmitted first on the RapidIO link.