Altera RapidIO II MegaCore Function - Manual (Page 195)

August 2014 Altera Corporation RapidIO II MegaCore Function
User Guide
7. Testbench
The RapidIO II IP core includes a demonstration testbench for your use. The testbench
demonstrates how to instantiate the IP core in a design and includes some simple
stimulus to control the user interfaces of the RapidIO II IP core.The purpose of the
supplied testbench is to provide an example of how to parameterize the IP core and
how to use the Avalon Memory-Mapped (Avalon-MM) and Avalon Streaming
(Avalon-ST) interfaces to generate and process RapidIO transactions.
The testbench demonstrates the following functions:
■ Port initialization process
■ Transmission, reception, and acknowledgment of packets with 8 to 256 bytes of
data payload
■ Support for 8-bit or 16-bit device ID fields
■ Reading from the software interface registers
■ Transmission and reception of multicast-event control symbols
The testbench also demonstrates how to connect your RapidIO II IP core variation to
an Altera Transceiver PHY Reset Controller IP core.
The RapidIO II IP core provides only a Verilog testbench. If you generate a VHDL IP
core variation, you must use a mixed-language simulator or create your own
testbench.
Testbench Overview
The testbench generates and monitors transactions on the Avalon-MM interfaces and
Avalon-ST interface. MAINTENANCE, Input/Output, or DOORBELL transactions are
generated if you select the corresponding modules during parameterization of the IP
core.
The testbench instantiates two symmetrical RapidIO II IP core variations, each
associated with an Altera Transceiver PHY Reset Controller IP core. One instance is
the Device Under Test (DUT), named rio_inst. The other instance acts as a RapidIO
link partner for the RapidIO DUT module and is referred to as the sister_rio module.
The two instances are interconnected through their high-speed serial interfaces. In the
testbench, each IP core’s td output is connected to the other IP core’s rd input.
The sister_rio module, named sis_rio_inst, responds to transactions initiated by the
DUT and generates transactions to which the DUT responds. Bus functional models
(BFM) are connected to the Avalon-MM and Avalon-ST interfaces of both the DUT
and sister_rio modules, to generate transactions to which the link partner responds
when appropriate, and to monitor the responses.
Figure 7–1 is a block diagram of the testbench in which all of the available
Avalon-MM interfaces are enabled. The two IP cores communicate with each other
using the RapidIO interface. The testbench initiates the following transactions at the
DUT and targets them to the sister_rio module:
■ SWRITE