Altera RapidIO II MegaCore Function - Manual (Page 76)

4–34 Chapter 4: Functional Description
Logical Layer Interfaces
RapidIO II MegaCore Function August 2014 Altera Corporation
User Guide
Table 4–14 lists the Maintenance Avalon-MM interface master port signals.
Initiating MAINTENANCE Read and Write Transactions
To initiate a MAINTENANCE read or write transaction on the RapidIO link, your system
executes a read or write transfer on the Maintenance Avalon-MM slave interface.
Refer to
“Maintenance Interface Transaction Examples” on page 4–38 for examples of
how the RapidIO II IP core converts Avalon-MM requests to RapidIO MAINTENANCE
request packets.
IP Core Actions
In response to incoming Avalon-MM requests to the Maintenance module slave
interface, the RapidIO II IP core Maintenance module generates MAINTENANCE requests
on the RapidIO link, by performing the following tasks:
■ For each incoming Avalon-MM read request, composes the RapidIO MAINTENANCE
read request packet
■ For each incoming Avalon-MM write request, composes the RapidIO MAINTENANCE
write request packet
■ Maintains status related to the composed MAINTENANCE packet to track responses
■ Presents the composed MAINTENANCE packet to the Transport layer for transmission
on the RapidIO link
1 At any time, the Maintenance module can maintain a maximum of 64 outstanding
MAINTENANCE
requests that can be MAINTENANCE reads, MAINTENANCE writes, or
port-write requests. The Maintenance module slave port asserts the
mnt_s_waitrequest signal to throttle incoming requests above the limit.
Defining the Maintenance Address Translation Windows
Two address translation windows available for interpreting incoming Avalon-MM
requests to the Maintenance module slave interface.
You must program the Tx Maintenance Window registers to support the address
ranges you wish to distinguish. The RapidIO II IP core Maintenance module
populates the following RapidIO Type 8 Request packet fields with values you
program for the relevant address translation window:
■ prio
■ destinationID
Table 4–14. Maintenance Avalon-MM Master Interface Signals
Signal Direction Description
usr_mnt_waitrequest Input Maintenance master wait request.
usr_mnt_read Output Maintenance master read request.
usr_mnt_write Output Maintenance master write request.
usr_mnt_address[31:0] Output Maintenance master address bus.
usr_mnt_writedata[31:0] Output Maintenance master write data bus.
usr_mnt_readdata[31:0] Input Maintenance master read data bus.
usr_mnt_readdatavalid Input Maintenance master read data valid.