Altera Video and Image Processing Suite - Manual (Page 102)

Address Register Description
27
Mode1 F0 Ancillary
Line
The line in field F0 to start inserting ancillary data packets.
28
Mode1 Valid
Video mode 1 valid. Set to indicate that this mode is valid and
can be used for video output.
29
ModeN Control ...
...
Table 4-23: Clocked Video Output II Registers
The rows in the table are repeated in ascending order for each video mode. All of the ModeN registers are write
only.
Address Register Description
0
Control • Bit 0 of this register is the
Go
bit:
• Setting this bit to 1 causes the CVO IP core start video
data output.
• Bits 3, 2, and 1 of the
Control
register are the interrupt
enables:
• Setting bit 1 to 1, enables the status update interrupt.
• Setting bit 2 to 1, enables the locked interrupt.
• Setting bit 3 to 1, enables the synchronization outputs
(
vid_sof
,
vid_sof_locked
,
vcoclk_div
).
• When bit 3 is set to 1, setting bit 4 to 1, enables frame
locking. The CVO IP core attempts to align its
vid_sof
signal to the
sof
signal from the CVI IP core.
1
Status • Bit 0 of this register is the
Status
bit.
• This bit is asserted when the CVO IP core is producing
data.
• Bit 1 of the
Status
register is unused.
• Bit 2 is the underflow sticky bit.
• When bit 2 is asserted, the output FIFO has
underflowed. The underflow sticky bit stays asserted
until a 1 is written to this bit.
• Bit 3 is the frame locked bit.
• When bit 3 is asserted, the CVO IP core has aligned its
start of frame to the incoming
sof
signal.
UG-VIPSUITE
2015.05.04
Clocked Video Interface Control Registers 4-43
Clocked Video Interface IP Cores Altera Corporation
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