Altera Video and Image Processing Suite - Manual (Page 87)

Signal Direction Description
is_sop
Output
dout
port Avalon-ST
startofpacket
signal. This signal is
asserted when the IP core is starting a new frame.
is_valid
Output
dout
port Avalon-ST
valid
signal. This signal is asserted
when the IP core produces data.
overflow
Output Clocked video overflow signal. A signal corresponding to
the overflow sticky bit of the
Status
register synchronized
to
vid_clk
. This signal is for information only and no
action is required if it is asserted.
Note: Present only if you turn on Use control port.
refclk_div
Output A single cycle pulse in-line with the rising edge of the h
sync.
sof
Output Start of frame signal. A change of 0 to 1 indicates the start
of the video frame as configured by the SOF registers.
Connecting this signal to a CVO IP core allows the
function to synchronize its output video to this signal.
sof_locked
Output Start of frame locked signal. When asserted, the
sof
signal
is valid and can be used.
status_update_int
Output
control
slave port Avalon-MM interrupt signal. When
asserted, the status registers of the IP core have been
updated and the master must read them to determine
what has occurred.
Note: Present only if you turn on Use control port.
vid_clk
Input Clocked video clock. All the video input signals are
synchronous to this clock.
vid_data
Input Clocked video data bus. This bus enables the transfer of
video data into the IP core.
vid_datavalid
Input Clocked video data valid signal. Assert this signal when a
valid sample of video data is present on
vid_data
.
vid_f
Input Clocked video field signal. For interlaced input, this signal
distinguishes between field 0 and field 1. For progressive
video, you must deassert this signal.
Note: For separate synchronization mode only.
vid_h_sync
Input Clocked video horizontal synchronization signal. Assert
this signal during the horizontal synchronization period of
the video stream.
Note: For separate synchronization mode only.
4-28 Clocked Video Interface Signals
UG-VIPSUITE
2015.05.04
Altera Corporation Clocked Video Interface IP Cores
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