Gamma Corrector IP Core................................................................................15-1
Gamma Corrector Parameter Settings....................................................................................................15-1
Gamma Corrector Signals........................................................................................................................ 15-2
Gamma Corrector Control Registers......................................................................................................15-3
Interlacer IP Core..............................................................................................16-1
Interlacer Parameter Settings...................................................................................................................16-2
Interlacer Signals........................................................................................................................................16-2
Interlacer Control Registers..................................................................................................................... 16-4
Scaler II IP Core.................................................................................................17-1
Nearest Neighbor Algorithm................................................................................................................... 17-1
Bilinear Algorithm.....................................................................................................................................17-2
Bilinear Algorithmic Description................................................................................................ 17-2
Polyphase and Bicubic Algorithm...........................................................................................................17-3
Double-Buffering........................................................................................................................... 17-5
Polyphase Algorithmic Description............................................................................................ 17-6
Choosing and Loading Coefficients............................................................................................ 17-6
Edge-Adaptive Scaling Algorithm...........................................................................................................17-8
Scaler II Parameter Settings......................................................................................................................17-9
Scaler II Signals........................................................................................................................................ 17-12
Scaler II Control Registers......................................................................................................................17-14
Video Switching IP Cores..................................................................................18-1
Mixer Layer Switching.............................................................................................................................. 18-2
Video Switching Parameter Settings....................................................................................................... 18-3
Video Switching Signals............................................................................................................................18-3
Video Switching Control Registers......................................................................................................... 18-5
Test Pattern Generator IP Cores.......................................................................19-1
Test Pattern.................................................................................................................................................19-1
Generation of Avalon-ST Video Control Packets and Run-Time Control.......................................19-3
Test Pattern Generator Parameter Settings............................................................................................19-4
Test Pattern Generator Signals................................................................................................................ 19-6
Test Pattern Generator Control Registers..............................................................................................19-8
Trace System IP Core........................................................................................ 20-1
Trace System Parameter Settings.............................................................................................................20-2
Trace System Signals................................................................................................................................. 20-3
Operating the Trace System from System Console...............................................................................20-4
Loading the Project and Connecting to the Hardware.............................................................20-5
Trace Within System Console......................................................................................................20-6
TCL Shell Commands................................................................................................................... 20-7
TOC-5
Altera Corporation
