Altera Video and Image Processing Suite User Manual
Page 276
a. Copy the verification files to a local directory and cd to the testbench directory.
>cp $(QUARTUS_ROOTDIR)/../ip/altera/vip/verification $ALTERA_VIDEO_VERIFICA-
TION >cd $ALTERA_VIDEO_VERIFICATION/testbench
b. Start the Qsys system integration tool from the Quartus II software (tools > Qsys or through
command line.
G:\altera\14.0\quartus\sopc_builder\bin>qsys-edit
c. Load the Qsys project. Double-click
tb.qsys
.
d. Update the IP search path by selecting from the Tools menu > Options > Add. Navigate to one
directory higher and into the dut directory.
e. Click Open, then Finish.
The system refreshes and shows the RGBtogreyscaleconvertor (in between Avalon-ST source and
sink BFMs), which is our example DUT. You can easily replaced this example by any other user IP
function.
Figure A-3: Qsys Dialog Box
f. Create the
tb.v
netlist from the Qsys project by selecting Generation, set Create simulation model
to Verilog. Select Generate. Close the generate completed dialog box, and exit Qsys.
Qsys has now generated the
tb.v
netlist and all the required simulation files.
A-8
Running the Tests
UG-VIPSUITE
2015.05.04
Altera Corporation
Avalon-ST Video Verification IP Suite