Altera Video and Image Processing Suite User Manual
Page 53
The first two registers of every control interface perform the following two functions (the others vary with
each control interface):
• Register 0 is the
Go
register. Bit zero of this register is the
Go
bit. A few cycles after the function comes
out of reset, it writes a zero in the
Go
bit (remember that all registers in Avalon-MM control slaves
power up in an undefined state).
• Although there are a few exceptions, most Video and Image Processing Suite IP cores stop at the
beginning of an image data packet if the
Go
bit is set to 0. This allows you to stop the IP core and to
program run-time control data before the processing of the image data begins. A few cycles after the
Go
bit is set by external logic connected to the control port, the IP core begins processing image data. If
the
Go
bit is unset while data is being processed, then the IP core stops processing data again at the
beginning of the next image data packet and waits until the
Go
bit is set by external logic.
• Register 1 is the
Status
register. Bit zero of this register is the
Status
bit; the function does not use all
other bits. The function sets the
Status
bit to 1 when it is running, and zero otherwise. External logic
attached to the control port must not attempt to write to the
Status
register.
The following pseudo-code illustrates the design of functions that double-buffer their control (that is, all
IP cores except the Gamma Corrector and some Scaler II parameterizations):
go = 0;
while (true)
{
read_non_image_data_packets();
status = 0;
while (go != 1)
wait;
read_control(); // Copies control to internal registers
status = 1;
send_image_data_header();
process_frame();
}
For IP cores that do not double buffer their control data, the algorithm described in the previous
paragraph is still largely applicable but the changes to the control register will affect the current frame.
Most Video and Image Processing Suite IP cores with a slave interface read and propagate non-image data
packets from the input stream until the image data header (0) of an image data packet has been received.
The status bit is then set to 0 and the IP core waits until the
Go
bit is set to 1 if it is not already. Once the
Go
bit is set to 1, the IP core buffers control data, sets its status bit back to 1, and starts processing image
data.
Note: There is a small amount of buffering at the input of each Video and Image Processing Suite IP core
and you must expect that a few samples are read and stored past the image data header even if the
function is stalled.
You can use the
Go
and
Status
registers in combination to synchronize changes in control data to the
start and end of frames. For example, suppose you want to build a system with a Gamma Corrector IP
core where the gamma look-up table is updated between each video frame.
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Avalon-MM Slave Interfaces
UG-VIPSUITE
2015.05.04
Altera Corporation
Interfaces