Altera Video and Image Processing Suite - Manual (Page 207)

Signal Direction Description
read_master_av_clock
Input
read_master
port
clock
signal. The interface operates on
the rising edge of the
clock
signal.
read_master_av_reset
Input
read_master
port reset signal. The interface asynchro‐
nously resets when this signal is high. You must deassert
this signal synchronously to the rising edge of the clock
signal.
read_master_av_address
Output
read_master
port Avalon-MM
address
bus. This bus
specifies a byte address in the Avalon-MM address space.
read_master_av_burstcount
Output
read_master
port Avalon-MM
burstcount
signal. This
signal specifies the number of transfers in each burst.
read_master_av_read
Output
read_master
port Avalon-MM
read
signal. The IP core
asserts this signal to indicate read requests from the
master to the system interconnect fabric.
read_master_av_readdata
Input
read_master
port Avalon-MM
readdata
bus. These
input lines carry data for read transfers.
read_master_av_readdata-
valid
Input
read_master
port Avalon-MM
readdatavalid
signal.
The system interconnect fabric asserts this signal when the
requested read data has arrived.
read_master_av_waitrequest
Input
read_master
port Avalon-MM
waitrequest
signal. The
system interconnect fabric asserts this signal to cause the
master port to wait.
write_master_av_clock
Input
write_master
port
clock
signal. The interface operates on
the rising edge of the
clock
signal.
write_master_av_reset
Input
write_master
port
reset
signal. The interface asynchro‐
nously resets when this signal is high. You must deassert
this signal synchronously to the rising edge of the
clock
signal.
write_master_av_address
Output
write_master
port Avalon-MM
address
bus. This bus
specifies a byte address in the Avalon-MM address space.
write_master_av_burstcount
Output
write_master
port Avalon-MM
burstcount
signal. This
signal specifies the number of transfers in each burst.
write_master_av_waitrequest
Input
write_master
port Avalon-MM
waitrequest
signal. The
system interconnect fabric asserts this signal to cause the
master port to wait.
write_master_av_write
Output
write_master
port Avalon-MM
write
signal. The IP core
asserts this signal to indicate write requests from the
master to the system interconnect fabric.
write_master_av_writedata
Output
write_master
port Avalon-MM
writedata
bus. These
output lines carry data for write transfers.
14-10 Frame Buffer Signals
UG-VIPSUITE
2015.05.04
Altera Corporation Frame Buffer IP Cores
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