Vid_data vid_datavalid – Altera Video and Image Processing Suite User Manual

Page 32

Advertising
background image

Clocked Video Output IP Cores

For the embedded synchronization format, the CVO IP cores insert the horizontal and vertical syncs and

field into the data stream during the horizontal blanking period.
The IP cores create a sample for each clock cycle on the

vid_data

bus.

There are two extra signals only used when connecting to the SDI IP core. They are

vid_trs

, which is

high during the 3FF sample of the TRS, and

vid_ln

, which produces the current SDI line number. These

are used by the SDI IP core to insert line numbers and cyclical redundancy checks (CRC) into the SDI

stream as specified in the 1.5 Gbps HD SDI and 3 Gbps SDI standards.
The CVO IP cores insert any ancillary packets (packets with a type of 13 or 0xD) into the output video

during the vertical blanking. The IP cores begin inserting the packets on the lines specified in its

parameters or mode registers (

ModeN Ancillary Line

and

ModeN F0 Ancillary Line

). The CVO IP

cores stop inserting the packets at the end of the vertical blanking.

Clocked Video Input IP Cores

The CVI IP cores support both 8 and 10-bit TRS and XYZ words. When in 10-bit mode, the IP cores

ignore the bottom 2 bits of the TRS and XYZ words to allow easy transition from an 8-bit system.

Table 2-1: XYZ Word Format

The XYZ word contains the synchronization information and the relevant bits of its format.

Bits

10-bit

8-bit

Description

Unused

[5:0]

[3:0]

These bits are not inspected by the CVI IP cores.

H (sync)

6

4

When 1, the video is in a horizontal blanking period.

V (sync)

7

5

When 1, the video is in a vertical blanking period.

F (field)

8

6

When 1, the video is interlaced and in field 1. When 0,

the video is either progressive or interlaced and in field

0.

Unused

9

7

These bits are not inspected by the CVI IP cores.

For the embedded synchronization format, the

vid_datavalid

signal indicates a valid BT656 or BT1120

sample. The CVI IP cores only read the

vid_data

signal when

vid_datavalid

is 1.

Figure 2-5: Vid_datavalid Timing

D0

D1

vid_data

vid_datavalid

UG-VIPSUITE

2015.05.04

Video Formats

2-5

Interfaces

Altera Corporation

Send Feedback

Advertising