Altera Video and Image Processing Suite - Manual (Page 180)

Signal Direction Description
control_byteenable
Output
control
slave port Avalon-MM
byteenable
bus. This bus
enables specific byte lane or lanes during transfers.
Each bit in
byteenable
corresponds to a byte in
writedata
and
readdata
.
• During writes,
byteenable
specifies which bytes are
being written to; the slave ignores other bytes.
• During reads,
byteenable
indicates which bytes the
master is reading. Slaves that simply return
readdata
with no side effects are free to ignore
byteenable
during reads.
edi_read_master_address
Output
edi_read_master
port Avalon-MM
address
bus. This
bus specifies a byte address in the Avalon-MM address
space.
edi_read_master_read
Output
edi_read_master
port Avalon-MM
read
signal. The IP
core asserts this signal to indicate read requests from the
master to the system interconnect fabric.
edi_read_master_burstcount
Output
edi_read_master
port Avalon-MM
burstcount
signal.
This signal specifies the number of transfers in each burst.
edi_read_master_readdata
Input
edi_read_master
port Avalon-MM
readdata
bus. These
input lines carry data for read transfers.
edi_read_master_readdata-
valid
Input
edi_read_master
port Avalon-MM
readdatavalid
signal. The system interconnect fabric asserts this signal
when the requested read data has arrived.
edi_read_master_waitrequest
Input
edi_read_master
port Avalon-MM
waitrequest
signal.
The system interconnect fabric asserts this signal to cause
the master port to wait.
ma_read_master_address
Output
ma_read_master
port Avalon-MM
address
bus. This bus
specifies a byte address in the Avalon-MM address space.
ma_read_master_read
Output
ma_read_master
port Avalon-MM
read
signal. The IP
core asserts this signal to indicate read requests from the
master to the system interconnect fabric.
ma_read_master_burstcount
Output
ma_read_master
port Avalon-MM
burstcount
signal.
This signal specifies the number of transfers in each burst.
ma_read_master_readdata
Input
ma_read_master
port Avalon-MM
readdata
bus. These
input lines carry data for read transfers.
ma_read_master_readdata-
valid
Input
ma_read_master
port Avalon-MM
readdatavalid
signal.
The system interconnect fabric asserts this signal when the
requested read data has arrived.
UG-VIPSUITE
2015.05.04
Deinterlacing Signals 12-21
Deinterlacing IP Cores Altera Corporation
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