Altera Video and Image Processing Suite User Manual

Page 117

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Signal

Direction

Description

din_N_valid

Input

din_N

port Avalon-ST

valid

signal. This signal identifies

the cycles when the port must input data.

dout_N_data

Output

dout

port Avalon-ST

data

bus. This bus enables the

transfer of pixel data out of the IP core.

dout_N_endofpacket

Output

dout_N

port Avalon-ST

endofpacket

signal. This signal

marks the end of an Avalon-ST packet.

dout_N_ready

Input

dout_N

port Avalon-ST

ready

signal. The downstream

device asserts this signal when it is able to receive data.

dout_N_startofpacket

Output

dout_N

port Avalon-ST

startofpacket

signal. This signal

marks the start of an Avalon-ST packet.

dout_N_valid

Output

dout_N

port Avalon-ST

valid

signal. The IP core asserts

this signal when it produces data.

Table 6-4: Alpha Signals for Alpha Blending Mixer IP Core

The table below lists the signals that are available only when you turn on Alpha blending in the Alpha Blending

Mixer parameter editor. These signals that are available only for Alpha Blending Mixer IP core.

Signal

Direction

Description

alpha_in_N_data

Input

alpha_in_N

port Avalon-ST

data

bus. This bus enables

the transfer of pixel data into the IP core.

alpha_in_N_endofpacket

Input

alpha_in_N

port Avalon-ST

endofpacket

signal. This

signal marks the end of an Avalon-ST packet.

alpha_in_N_ready

Output

alpha_in_N

port Avalon-ST

ready

signal. The IP core

asserts this signal when it is able to receive data.

alpha_in_N_startofpacket

Input

alpha_in_N

port Avalon-ST

startofpacket

signal. This

signal marks the start of an Avalon-ST packet.

alpha_in_N_valid

Input

alpha_in_N

port Avalon-ST

valid

signal. This signal

identifies the cycles when the port must insert data.

Table 6-5: Mixer II Signals

The table below lists the signals for Mixer II IP core.

Signal

Direction

Description

reset

Input

The IP core asynchronously resets when you assert this

signal. You must deassert this signal synchronously to the

rising edge of the clock signal.

clock

Input

The main system clock. The IP core operates on the rising

edge of this signal.

control_address

Input

control

slave port Avalon-MM

address

bus. This bus

specifies a word offset into the slave address space.

6-6

Video Mixing Signals

UG-VIPSUITE

2015.05.04

Altera Corporation

Video Mixing IP Cores

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