Altera Video and Image Processing Suite - Manual (Page 140)

Signal Direction Description
reset
Input The IP core asynchronously resets when this signal is high.
You must deassert this signal synchronously to the rising
edge of the clock signal.
dinN_data
Input
dinN
port Avalon-ST
data
bus. This bus enables the
transfer of pixel data into the IP core.
dinN_endofpacket
Input
dinN
port Avalon-ST
endofpacket
signal. This signal
marks the end of an Avalon-ST packet.
dinN_ready
Output
dinN
port Avalon-ST
ready
signal. This signal indicates
when the IP core is ready to receive data.
dinN_startofpacket
Input
dinN
port Avalon-ST
startofpacket
signal. This signal
marks the start of an Avalon-ST packet.
dinN_valid
Input
dinN
port Avalon-ST
valid
signal. This signal identifies
the cycles when the port must enter data.
doutN_data
Output
doutN
port Avalon-ST
data
bus. This bus enables the
transfer of pixel data out of the IP core.
doutN_endofpacket
Output
doutN
port Avalon-ST
endofpacket
signal. This signal
marks the end of an Avalon-ST packet.
doutN_ready
Input
doutN
port Avalon-ST
ready
signal. The downstream
device asserts this signal when it is able to receive data.
doutN_startofpacket
Output
doutN
port Avalon-ST
startofpacket
signal. This signal
marks the start of an Avalon-ST packet.
doutN_valid
Output
doutN
port Avalon-ST
valid
signal. The IP core asserts
this signal when it produces data.
9-6 Color Plane Sequencer Signals
UG-VIPSUITE
2015.05.04
Altera Corporation Color Plane Sequencer IP Core
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