Altera Video and Image Processing Suite - Manual (Page 96)

Address Register Description
1
Status • Bit 0 of this register is the
Status
bit.
• This bit is asserted when the CVI IP core is producing
data.
• Bits 5, 2, and 1 of the
Status
register are unused.
• Bits 6, 4, and 3 are the resolution valid bits.
• When bit 3 is asserted, the
SampleCount
register is
valid.
• When bit 4 is asserted, the
F0LineCount
register is
valid.
• When bit 6 is asserted, the
F1LineCount
register is
valid.
• Bit 7 is the interlaced bit:
• When asserted, the input video stream is interlaced.
• Bit 8 is the stable bit:
• When asserted, the input video stream has had a
consistent line length for two of the last three lines.
• Bit 9 is the overflow sticky bit:
• When asserted, the input FIFO has overflowed. The
overflow sticky bit stays asserted until a 1 is written to
this bit.
• Bit 10 is the resolution bit:
• When asserted, indicates a valid resolution in the
sample and line count registers.
2
Interrupt
Bits 2 and 1 are the interrupt status bits:
• When bit 1 is asserted, the status update interrupt has
triggered.
• When bit 2 is asserted, the stable video interrupt has
triggered.
• The interrupts stay asserted until a 1 is written to these
bits.
3
Used Words
The used words level of the input FIFO.
4
Active Sample Count
The detected sample count of the video streams excluding
blanking.
5
F0 Active Line Count
The detected line count of the video streams F0 field
excluding blanking.
6
F1 Active Line Count
The detected line count of the video streams F1 field
excluding blanking.
UG-VIPSUITE
2015.05.04
Clocked Video Interface Control Registers 4-37
Clocked Video Interface IP Cores Altera Corporation
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