Altera Video and Image Processing Suite - Manual (Page 181)

Signal Direction Description
ma_read_master_waitrequest
Input
ma_read_master
port Avalon-MM
waitrequest
signal.
The system interconnect fabric asserts this signal to cause
the master port to wait.
motion_read_master_address
Output
motion_read_master
port Avalon-MM
address
bus.
This bus specifies a byte address in the Avalon-MM
address space.
motion_read_master_read
Output
motion_read_master
port Avalon-MM
read
signal. The
IP core asserts this signal to indicate read requests from
the master to the system interconnect fabric.
motion_read_master_
burstcount
Output
motion_read_master
port Avalon-MM
burstcount
signal. This signal specifies the number of transfers in each
burst.
motion_read_master_readdata
Input
motion_read_master
port Avalon-MM
readdata
bus.
These input lines carry data for read transfers.
motion_read_master_
readdatavalid
Input
motion_read_master
port Avalon-MM
readdatavalid
signal. The system interconnect fabric asserts this signal
when the requested read data has arrived.
motion_read_master_
waitrequest
Input
motion_read_master
port Avalon-MM
waitrequest
signal. The system interconnect fabric asserts this signal to
cause the master port to wait.
write_master_address
Output
write_master
port Avalon-MM
address
bus. This bus
specifies a byte address in the Avalon-MM address space.
write_master_write
Output
write_master
port Avalon-MM
write
signal. The IP core
asserts this signal to indicate write requests from the
master to the system interconnect fabric.
write_master_burstcount
Output
write_master
port Avalon-MM
burstcount
signal. This
signal specifies the number of transfers in each burst.
write_master_writedata
Output
write_master
port Avalon-MM
writedata
bus. These
output lines carry data for write transfers.
write_master_waitrequest
Input
write_master
port Avalon-MM
waitrequest
signal. The
system interconnect fabric asserts this signal to cause the
master port to wait.
motion_write_master_address
Output
motion_write_master
port Avalon-MM
address
bus.
This bus specifies a byte address in the Avalon-MM
address space.
motion_write_master_write
Output
motion_write_master
port Avalon-MM
write
signal.
The IP core asserts this signal to indicate write requests
from the master to the system interconnect fabric.
12-22 Deinterlacing Signals
UG-VIPSUITE
2015.05.04
Altera Corporation Deinterlacing IP Cores
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