Altera Video and Image Processing Suite User Manual

Page 149

Advertising
background image

Signal

Direction

Description

din_endofpacket

Input

din

port Avalon-ST

endofpacket

signal. This signal

marks the end of an Avalon-ST packet.

din_ready

Output

din

port Avalon-ST

ready

signal. This signal indicates

when the IP core is ready to receive data.

din_startofpacket

Input

din

port Avalon-ST

startofpacket

signal. This signal

marks the start of an Avalon-ST packet.

din_valid

Input

din

port Avalon-ST

valid

signal. This signal identifies the

cycles when the port must insert data.

dout_data

Output

dout

port Avalon-ST

data

bus. This bus enables the

transfer of pixel data out of the IP core.

dout_endofpacket

Output

dout

port Avalon-ST

endofpacket

signal. This signal

marks the end of an Avalon-ST packet.

dout_ready

Input

dout

port Avalon-ST

ready

signal. The downstream

device asserts this signal when it is able to receive data.

dout_startofpacket

Output

dout

port Avalon-ST

startofpacket

signal. This signal

marks the start of an Avalon-ST packet.

dout_valid

Output

dout

port Avalon-ST

valid

signal. The IP core asserts this

signal when it produces data.

control_address

Input

control

slave port Avalon-MM

address

bus. This bus

specifies a word offset into the slave address space.

control_write

Input

control

slave port Avalon-MM

write

signal. When you

assert this signal, the

control

port accepts new data from

the

writedata

bus.

control_writedata

Input

control

slave port Avalon-MM

writedata

bus. The IP

core uses these input lines for write transfers.

control_read

Output

control

slave port Avalon-MM

read

signal. When you

assert this signal, the control port produces new data at

readdata

.

control_readdata

Output

control

slave port Avalon-MM

readdatavalid

bus. The

IP core uses these output lines for read transfers.

control_readdatavalid

Output

control

slave port Avalon-MM

readdata

bus. The IP

core asserts this signal when the

readdata

bus contains

valid data in response to the read signal.

control_waitrequest

Output

control

slave port Avalon-MM

waitrequest

signal.

UG-VIPSUITE

2015.05.04

Color Space Conversion Signals

10-9

Color Space Conversion IP Cores

Altera Corporation

Send Feedback

Advertising