Interlacer ip core, Interlacer ip core -1 – Altera Video and Image Processing Suite User Manual
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Interlacer IP Core
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2015.05.04
UG-VIPSUITE
The Interlacer IP core converts progressive video to interlaced video by dropping half the lines of
incoming progressive frames.
The Interlacer IP core generates an interlaced stream by dropping half the lines of each progressive input
frame. The IP core drops odd and even lines in successive order to produce an alternating sequence of F0
and F1 fields. The output field rate is consequently equal to the input frame rate.
The Interlacer IP core handles changing input resolutions by reading the content of Avalon-ST Video
control packets. The IP core supports incoming streams where the height of the progressive input frames
is an odd value. In such a case, the height of the output F0 fields are one line higher than the height of the
output F1 fields.
When the input stream is already interlaced, the IP core either discards the incoming interlaced fields or
propagates the fields without modification, based on the compile time parameters you specify. When you
turn on Run-time control in the parameter editor, you can also deactivate the Interlacer IP core at run
time to prevent the interlacing and propagate a progressive video stream without modification.
At start up or after a change of input resolution, the Interlacer IP core begins the interlaced output stream
by dropping odd lines to construct a F0 field or by dropping even lines to construct a F1 field, based on
the compile time parameters you specify.
Alternatively, when you turn on Control packets override field selection parameter and the interlace
nibble indicates that the progressive input previously went through a deinterlacer (0000 or 0001), the
Interlacer IP core produces:
• a F0 field if the interlace nibble is 0000
• a F1 field if the interlace nibble is 0001
Note: For most systems, turn off Control packets override field selection parameter to guarantee the
Interlacer IP core produces a valid interlaced video output stream where F0 and F1 fields alternate
in regular succession.
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