Altera Video and Image Processing Suite - Manual (Page 200)

• The writer uses one buffer to store input pixels.
• The reader locks the second buffer that reads the output pixels from the memory.
• The third buffer is a spare buffer that allows the input and the output sides to swap buffers asynchro‐
nously. The spare buffer can be clean or dirty.
• Considered clean if it contains a fresh frame that has not been sent.
• Considered dirty if it contains an old frame that has already been sent by the reader component.
• When the writer completes storing a frame in memory, it swaps its buffer with the spare buffer if the
spare buffer is dirty.
• The buffer locked by the writer becomes the new spare buffer and is clean because it contains a fresh
frame.
• If the spare buffer is already clean when the writer completes writing the current input frame:
• If dropping frames is allowed—the writer drops the newly received frame and overwrites its buffer
with the next incoming frame.
• If dropping frames is not allowed—the writer stalls until the reader completes its frame and
replaces the spare buffer with a dirty buffer.
• When the reader completes reading and produces a frame from memory, it swaps its buffer with the
spare buffer if the spare buffer is clean.
• The buffer locked by the reader becomes the new spare buffer; and is dirty because it contains an old
frame that has been sent previously.
• If the spare buffer is already dirty when the reader completes the current output frame:
• If repeating frames is allowed—the reader immediately repeats the frame that has just been sent.
• If repeating frames is not allowed—the reader stalls until the writer completes its frame and
replaces the spare buffer with a clean buffer.
Locked Frame Rate Conversion
The locked frame rate conversion allows the IP core to synchronize the input and output frame rates
through an Avalon-MM slave interface.
The decision to drop and repeat frames for triple-buffering is based on the status of the spare buffer.
Because the input and output sides are not tightly synchronized, the behavior of the Frame Buffer IP core
is not completely deterministic and can be affected by the burstiness of the data in the video system. This
may cause undesirable glitches or jerky motion in the video output, especially if the data path contains
more than one triple buffer.
By controlling the dropping or repeating behavior, the IP core can keep the input and output synchron‐
ized. To control the dropping or repeating behavior, you must select triple-buffering mode and turn on
Support for locked frame rate conversion in the Frame Buffer parameter editor.
You can select and change the input and output rates at run time. Using the slave interface, it is also
possible to enable or disable synchronization at run time to switch between the user-controlled and flow-
controlled triple-buffering algorithms as necessary.
Handling of Avalon-ST Video Control Packets
The Frame Buffer IP core stores non-image data packets in memory.
UG-VIPSUITE
2015.05.04
Locked Frame Rate Conversion 14-3
Frame Buffer IP Cores Altera Corporation
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