Altera Video and Image Processing Suite - Manual (Page 120)

Table 6-7: Mixer II Control Register Map
The table below describes the control register map for Mixer II IP core.
Address Register Description
0
Control
Bit 0 of this register is the
Go
bit, all other bits are unused.
Setting this bit to 0 causes the IP core to stop the next time
control information is read.
1
Status
Bit 0 of this register is the
Status
bit, all other bits are unused.
2
Interrupt
Unused.
3
Input 0 X
X offset in pixels from the left edge of the background layer to
the left edge of input 0.
Y offset in pixels from the top edge of the background layer to
the top edge of input 0.
5
Input 0 enable • Set to bit 0 to enable Input 0.
• Set to bit 1 to enable consume mode.
6 Reserved Reserved for future use.
7 Reserved Reserved for future use.
8
Input 1 X
X offset in pixels from the left edge of the background layer to
the left edge of input 1.
9
Input 1 Y
Y offset in pixels from the top edge of the background layer to
the top edge of input 1.
10
Input 1 enable • Set to bit 0 to enable Input 1.
• Set to bit 1 to enable consume mode.
11 Reserved Reserved for future use.
12 Reserved Reserved for future use.
13
Input 2 X
X offset in pixels from the left edge of the background layer to
the left edge of input 2.
14
Input 2 Y
Y offset in pixels from the top edge of the background layer to
the top edge of input 2.
15
Input 2 enable • Set to bit 0 to enable Input 2.
• Set to bit 1 to enable consume mode.
16 Reserved Reserved for future use.
17 Reserved Reserved for future use.
18
Input 3 X
X offset in pixels from the left edge of the background layer to
the left edge of input 3.
19
Input 3 Y
Y offset in pixels from the top edge of the background layer to
the top edge of input 3.
UG-VIPSUITE
2015.05.04
Video Mixing Control Registers 6-9
Video Mixing IP Cores Altera Corporation
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